Field of the Disclosure
Embodiments of the present disclosure generally relate to the fabrication of integrated circuits. More specifically, embodiments disclosed herein relate to methods for controlling substrate outgassing.
Description of the Related Art
The manufacture of modern logic, memory, or integrated circuits typically requires more than four hundred process steps. A number of these steps are thermal processes that raise the temperature of the semiconductor substrate to a target value to induce rearrangement in the atomic order or chemistry of thin surface films (e.g., diffusion, oxidation, recrystallization, salicidation, densification, flow).
Ion implementation is a method for the introduction of chemical impurities in semiconductor substrates to form the p-n junctions necessary for field effect or bipolar transistor fabrication. Such impurities include P-type dopants, such as boron, aluminum, gallium, beryllium, magnesium, and zinc, and N-type dopants such as phosphorus, arsenic, antimony, bismuth, selenium, and tellurium. Ion implantation of chemical impurities disrupts the crystallinity of the semiconductor substrate over the range of the implant. At low energies, relatively little damage occurs to the substrate. However, the implanted dopants will not come to rest on electrically active sites in the substrate. Therefore, an anneal is required to restore the crystallinity of the substrate and drive the implanted dopants onto electrically active crystal sites.
During the processing of the substrate in, for example, an RTP chamber, the substrate may tend to outgas impurities implanted therein. These outgassed impurities may be the dopant material, a material derived from the dopant material, or any other material that may escape the substrate during the annealing process, such as the sublimation of silicon. The outgassed impurities may deposit on the colder walls and on the reflector plate of the chamber. This deposition may interfere with temperature pyrometer readings and with the radiation distribution fields on the substrate, which in turn affects the temperature at which the substrate is annealed. Deposition of the outgassed impurities may also cause unwanted particles on the substrates and may also generate slip lines on the substrate. Depending on the chemical composition of the deposits, the chamber is taken offline for a wet clean process.
Furthermore, one of the biggest challenges for III-V CMOS (FinFET, TFET) mass production is to control the outgassing from the substrates after a III-V epitaxial growth process and/or an etch clean process. Limitations in current outgassing control include that the thermal back process (>200 degrees Celsius) in either a process chamber or an etch chamber is not suitable after a III-V epitaxial growth or etch process as longer bake times for each substrate is necessary to drive out arsenic related outgassing gasses from the substrate surface and throughput is lowered. Furthermore, a long N2 purge/pump cycle is less efficient and has a large impact on throughput. Testing has been performed on the prior known methods and results indicate that after ten cycles of pump/purge, arsenic outgassing was still detected at 1.9 parts per billion.
Absolute zero parts per billion (ppb) outgassing is typically desired for arsenic residuals due to arsenic toxicity. To minimize toxicity from arsenic outgassing during subsequent handling and processing of substrates, there is a need for an improved method for controlling substrate outgassing.